Custom Layout Engineer - Infinecs Systems Sdn. Bhd.
- George Town, Penang, Malaysia
- Apply by: Jan 01, 2026
- 1 Vacancy
- Local Candidates (Malaysia)
- Shift: First Shift (Morning)
- Career Level: Experienced Professional
- Degree: Graduate
- Experience: Year
- Full Time/Permanent
- Work from Office
Job Description
Responsibilities:
• Responsible for VLSI component physical layout and data entry, translating schematics into
layout geometry at cell/fab/module level.
• Develop and prepare multi-dimensional layouts and detailed drawings of semiconductor
devices.
• Perform cell/module/chip level floor planning, manual placement, and routing, as well as
layout verification (such as LVS, DRC, Antenna & others), and LVS/DRC/RV errors clean-up &
fixes.
• Build the optimized layout, perform ECO and LCO changes within broadly defined physical
parameters.
Requirements:
• Bachelor’s degree in Electronic/Electrical/Computer engineering or Equivalent with
fundamental background in VLSI layout graphical design.
• At least 3 years of working experience in related field is required for this position.
• Familiar with basic EDA tools for manual graphical layout entry.
• Familiar with VLSI design knowledge to enable understanding in performing the layout tasks.
Possess outstanding debug skills.
• Proficient in Cadence Virtuoso and physical verification tool such as Synopsys ICV/Hercules
and/or Mentor Calibre is a must.
• Technologies: 7nm, 10nm, 14nm,16nm, 28nm, 32nm and 40nm. Experienced with Finfet
cutting edge technology would be an added advantage.
• Knowledge of IR drop, and EM analysis is a Plus.
• Experience in scripting such as Perl and Skill is a Plus.
• Excellent verbal and written communication skills are required.
• Excellent interpersonal and analytical skills with the ability to work independently.
• Highly motivated, excellent team spirit, product, and customer oriented.
• Responsible for VLSI component physical layout and data entry, translating schematics into
layout geometry at cell/fab/module level.
• Develop and prepare multi-dimensional layouts and detailed drawings of semiconductor
devices.
• Perform cell/module/chip level floor planning, manual placement, and routing, as well as
layout verification (such as LVS, DRC, Antenna & others), and LVS/DRC/RV errors clean-up &
fixes.
• Build the optimized layout, perform ECO and LCO changes within broadly defined physical
parameters.
Requirements:
• Bachelor’s degree in Electronic/Electrical/Computer engineering or Equivalent with
fundamental background in VLSI layout graphical design.
• At least 3 years of working experience in related field is required for this position.
• Familiar with basic EDA tools for manual graphical layout entry.
• Familiar with VLSI design knowledge to enable understanding in performing the layout tasks.
Possess outstanding debug skills.
• Proficient in Cadence Virtuoso and physical verification tool such as Synopsys ICV/Hercules
and/or Mentor Calibre is a must.
• Technologies: 7nm, 10nm, 14nm,16nm, 28nm, 32nm and 40nm. Experienced with Finfet
cutting edge technology would be an added advantage.
• Knowledge of IR drop, and EM analysis is a Plus.
• Experience in scripting such as Perl and Skill is a Plus.
• Excellent verbal and written communication skills are required.
• Excellent interpersonal and analytical skills with the ability to work independently.
• Highly motivated, excellent team spirit, product, and customer oriented.
Benefits
.
Skills Required
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